Section: New Results

Modeling hierarchical platform memory performance with microbenchmarks

Bertrand Putigny developed a new memory performance model based on micro-benchmarks during his PhD. He transforms parallel codes such as OpenMP into memory access skeleton before predicting memory buffer states in caches and using benchmarks outputs to predict the runtime. This model successfully predict the performance behavior of several memory-bound kernels [26] .

We also used this model to study the impact of memory caches on the performance on intra-node MPI communication [27] .